1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to structures and manufacturing methods for forming through-silicon vias.
2. Description of the Related Art
In recent years, the device features of modern, ultra-high density integrated circuits have been steadily decreasing in size in an effort to enhance the overall speed, performance, and functionality of the circuit. As a result, the semiconductor industry has experience tremendous growth due to the significant and ongoing improvements in integration density of a variety of electronic components, such as transistors, capacitors, diodes, and the like. These improvements have primarily come about due to a persistent and successful effort to reduce the critical dimension—i.e., minimum feature size—of components, directly resulting in the ability of process designers to integrate more and more components into a given area of a semiconductor chip.
Improvements in integrated circuit design have been essentially two-dimensional (2D)—that is, the improvements have been related primarily to the layout of the circuit on the surface of a semiconductor chip. However, as device features are being aggressively scaled, and more semiconductor components are being fit onto the surface of a single chip, the required number of electrical interconnects necessary for circuit functionality dramatically increases, resulting in an overall circuit layout that is increasingly becoming more complex and more densely packed. Furthermore, even though improvements in photolithography processes have yielded significant increases in the integration densities of 2D circuit designs, simple reduction in feature size is rapidly approaching the limit of what can presently be achieved in only two dimensions.
As the number of electronic devices on single chip rapidly increases, three-dimensional (3D) integrated circuit layouts, or stacked chip design, have been utilized for some semiconductor devices in an effort to overcome some of the feature size and density limitations associated with 2D layouts. Typically, in a 3D integrated circuit design, two or more semiconductor dies are bonded together, and electrical connections are formed between each die. One method of facilitating the chip-to-chip electrical connections is by use of so-called through-silicon vias, or TSV's. A TSV is a vertical electrical connection that passes completely through a silicon wafer or die, allowing for more simplified interconnection of vertically aligned electronic devices, thereby significantly reducing integrated circuit layout complexity as well as the overall dimensions of a multi-chip circuit. A typical prior art process for forming TSV's is illustrated in FIGS. 1a-1f, and will now be discussed in detail below.
FIG. 1a is a schematic cross-sectional view depicting one stage in the formation of a TSV in accordance with an illustrative prior art process. As shown in FIG. 1a, a semiconductor chip or wafer 100 may comprise a substrate 101, which may represent any appropriate carrier material above which may be formed a semiconductor layer 102. Additionally, a plurality of schematically depicted active and/or passive circuit elements 103, such as transistors, capacitors, resistors and the like, may be formed in and above the semiconductor layer 102, in which case the semiconductor layer 102 may also be referred to as a device layer 102. Depending on the overall design strategy of the wafer 100, the substrate 101 may in some embodiments be comprised of a substantially crystalline substrate material (i.e., bulk silicon), whereas in other embodiments the substrate 101 may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer 101a may be provided below the device layer 102. It should be appreciated that the semiconductor/device layer 102, even if comprising a substantially silicon-based material layer, may include other semiconducting materials, such as germanium, carbon and the like, in addition to appropriate dopant species for establishing the requisite active region conductivity type for the circuit elements 103.
FIG. 1a also illustrates a contact structure layer 104, which may be formed above the device layer 102 so as to provide electrical interconnects between the circuit elements 103 and a metallization system (not shown) to be formed above the device layer 102 during subsequent processing steps. For example, one or more interlayer dielectric (ILD) layers 104a may be formed above the device layer 102 so as to electrically isolate the respective circuit elements 103. The ILD layer 104a may comprise, for example, silicon dioxide, silicon nitride, silicon oxynitride, and the like, or a combination of these commonly used dielectric materials. Furthermore, depending on the device design and overall process flow requirements, the interlayer dielectric layer 104a may also comprise suitably selected low-k dielectric materials, such as porous silicon dioxide, organosilicates, organic polyimides, and the like. Thereafter, the ILD layer 104a may be patterned to form a plurality of via openings, each of which may be filled with a suitable conductive material such as tungsten, copper, nickel, silver, cobalt and the like (as well as alloys thereof), thereby forming contact vias 105. Additionally, in some embodiments, trench openings may also be formed in the ILD layer 104a, which may thereafter be filled with a similar conductive material such as noted for the contact vias 105 above, thereby forming conductive lines 106.
As shown in FIG. 1a, in certain embodiments, a hardmask layer 107, which may act as a stop layer for a subsequently performed chemical mechanical polishing (CMP) process, may thereafter be formed above the contact structure layer 104. The hardmask layer 107 may comprise a dielectric material having an etch selectivity relative to at least the material comprising the upper surface portion of the ILD layer 104a, such as silicon nitride, silicon oxynitride, and the like. In some illustrative embodiments, the hardmask layer 107 may be formed above the contact structure layer 104 by performing a suitable deposition processes based on parameters well known in the art, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, and the like. Thereafter, a patterned resist mask layer 108 may be formed above the hardmask layer 107 based on typical photolithography processes, such as exposure, baking, developing, and the like, so as to provide openings 108a in the mask layer 108, thereby exposing the hardmask layer 107.
FIG. 1b shows the illustrative prior art process of FIG. 1a in a further manufacturing stage, wherein an etch process 109 is performed to create TSV openings 110 in the wafer 100. As shown in FIG. 1b, the patterned resist mask layer 108 may be used as an etch mask during the etch process 109 to form openings in the hardmask layer 107, and to expose the ILD layer 104a of the contact structure layer 104. Thereafter, the etch process 109 may be continued, and the patterned mask layer 108 and patterned hardmask layer 107 may be used as mask elements to form the TSV openings 110 through the contact structure layer 104, through the device layer 102, and into the substrate 101. In certain embodiments, the etch process 109 may be a substantially anisotropic etch process, such as a deep reactive ion etch (REI), and the like. Depending on the chip design considerations and etch parameters employed during the etch process 109, the sidewalls 110s of the TSV openings 110 may be substantially vertical with respect to the front and back surfaces 100f, 100b of the wafer 100 (as shown in FIG. 1b), whereas in some embodiments the sidewalls 110s may be slightly tapered, depending on the depth of the TSV openings 110 and the specific etch recipe used to perform the etch process 109. Moreover, since the TSV openings 110 may pass through and/or into a plurality of different material layers, such as the ILD layer 104a, the device layer 102, a buried insulation layer 101a (when used), and the substrate 101, the etch process 109 may be substantially non-selective with respect to material type, such that a single etch recipe may be used throughout the duration of the etch.
Depending on the overall processing and chip design parameters, the openings 110 may have a width dimension 110w ranging from 1-10 μm, a depth dimension 110d ranging from 5-50 μm or even more, and an aspect ratio—i.e., depth-to-width ratio—ranging between 4 and 25. In one embodiment, the width dimension 110w may be approximately 5 μm, the depth dimension 110d may be approximately 50 μm, and the aspect ratio approximately 10. Typically, however, and as shown in FIG. 1b, the TSV openings 110 do not, at this stage of fabrication, extend through the full thickness of the substrate 101, but instead stop short of the back surface 100b of the wafer 100. For example, in some embodiments, the etch process 109 is continued until the bottom surfaces 110b of the TSV openings 110 come within a range of approximately 1-20 μm of the back surface 100b. Additionally, and as will be discussed in further detail below, after the completion of processing activities above the front side 100f of the wafer 100, such as processing steps to form a metallization system above the contact structure layer 104 and the like, the wafer 100 is thinned from the back side 100b so as to expose the finished TSV's 120 (see FIG. 1f).
FIG. 1c shows a further advanced step of the illustrative prior art method illustrated in FIG. 1b after the patterned resist mask layer 108 has been removed from above the hardmask layer 107. Depending on the overall chip configuration and design considerations, an isolation layer 111 may be formed on the exposed surfaces of the TSV openings 100 so as to eventually electrically isolate the finished TSV's 120 (see FIG. 1f) from the substrate 101, the device layer 102, and/or the contract structure layer 104. As shown in FIG. 1c, the isolation layer 111 may be formed above all exposed surfaces of the wafer 100, including the upper surface 107u of the hardmask layer 107, and the sidewall and bottom surfaces 110s, 110b of the TSV openings 110. In certain embodiments, the isolation layer 111 may be formed by performing a suitable conformal deposition process 131 so as to deposit an appropriate dielectric insulating material layer having a substantially uniform thickness on the exposed surfaces of the TSV openings 110.
For example, in some embodiments, the isolation layer 111 may be formed of silicon dioxide, and the deposition process 131 may be any one of several deposition techniques well known in the art, such as low-pressure chemical vapor deposition (LPCVD), atmospheric-pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In certain embodiments, the isolation layer 111 may comprise silicon dioxide, and may be deposited based on tetraethylorthosilicate (TEOS) and O3 (ozone) using LPCVD or PECVD processes. Additionally, the as-deposited thickness of the isolation layer 111 may be as required to ensure that the TSV 120 (see FIG. 1f) is electrically isolated from the surrounding layers of the wafer 100. For example, in some illustrative embodiments the isolation layer 111 may range in thickness from 20-100 nm, or even greater.
FIG. 1d depicts the illustrative prior art method of FIG. 1c after a barrier layer 112 has been formed above the wafer 100. In some embodiments, the barrier layer 112 may serve to prevent the conductive material comprising the finished TSV's 120 (see FIG. 10 from diffusing into and/or through the isolation layer 111, or into and/or through the ILD layer 104a, a situation that could significantly affect the overall performance of the circuit elements 103, the contact vias 105, and/or the conductive lines 106. Furthermore, the barrier layer 112 may also act as an adhesion layer, thereby potentially enhancing that overall bond between the contact material of the finished TSV's 120 and the underlying dielectric isolation layer 111.
As shown in FIG. 1d, the barrier layer 112 may be formed above all exposed surfaces of the isolation layer 111, including the exposed surfaces inside of the TSV openings 110. In certain illustrative embodiments, the barrier layer 112 may be deposited above the isolation layer 111 by performing a substantially conformal deposition process 132, such as CVD, PVD, ALD (atomic layer deposition) and the like. Depending on device requirements and TSV design parameters, the barrier layer 112 may comprise any one of a number of suitable barrier layer materials well known in the art to reduce and/or resist the diffusion of metal into a surrounding dielectric, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), and the like. Furthermore, due to the relatively large width 110w of the TSV openings 110 as compared to a contact via used to form an electrical interconnection to a typical integrated circuit element—such as the contact vias 105—the thickness of the barrier layer 112 may not be critical to the overall performance characteristics of the TSV's 120 (see FIG. 10. Accordingly, the thickness of the barrier layer 112 may in some illustrative embodiments range between 2 nm and 20 nm, depending on the material type and deposition method used to form the barrier layer 112.
After the barrier layer 112 has been formed above the exposed surfaces of the isolation layer 111, a layer of conductive contact material 113 may then be formed above the wafer 100 so as to completely fill the TSV openings 110, as shown in FIG. 1e. Depending on the TSV design requirements, the layer of conductive contact material 113 may be substantially comprised of copper, or in certain embodiments may comprise a suitable copper alloy. In some embodiments, the TSV openings 110 may be filled with the layer of conductive contact material 113 based on a substantially “bottom-up” deposition process 133 well known to those skilled in the art, such as a suitably designed electrochemical plating (ECP) process and the like, thereby reducing the likelihood that voids may be formed and/or trapped in the finished TSV's 120 (see FIG. 1f). In other illustrative embodiments, an electroless plating process may be employed. Additionally, and depending on the type of material used for the barrier layer 112 and the type of deposition process 133 used to fill the TSV openings 110, a seed layer (not shown) may be formed on the barrier layer 112 prior to performing the deposition process 133. In certain embodiments, the optional seed layer may be deposited using a highly conformal deposition process, such as sputter deposition, ALD, and the like, and may have a thickness ranging from approximately 5-10 nm. However, in other illustrative embodiments, the thickness of the barrier layer 133 may be even greater—for example, from 10-15 nm—whereas in still other embodiments, the thickness may be even less—for example, from 1-5 nm. Depending on the processing requirements, still other barrier layer thicknesses may be used.
It should be noted that, as a result of the “bottom-up” deposition process 133 used to fill the TSV openings 110 in some prior art processes, depressions 114 in the layer of conductive contact material 113 having a depth 114a may be present above each of the TSV openings 110 after completion of the deposition process 133. Accordingly, as shown in FIG. 1e, a significant amount of material “overburden” 113b, or additional thickness, may need to be deposited outside of the TSV openings 110 and above the upper horizontal surfaces 100s of the wafer 100 to ensure that the TSV openings 110 are completely filled with the layer of conductive contact material 113. In some embodiments, the depth 114a may be as much as one-half of the thickness of the overburden 113b, or even greater. Furthermore, in order to ensure that the depth 114a of the depressions 114 in the conductive contact material layer 113 does not encroach into the TSV openings 110, the overburden 113b may need to at least equal, if not exceed, the depth 114a. Depending on the width 110w, depth 110d, and aspect ratio of the TSV openings 110, the overburden 113b may in some illustrative embodiments range from 1-3 μm, or even greater. However, it should be noted that when such a large conductive contact layer overburden thickness is necessary in order to ensure complete filling of the TSV openings 110, the effectiveness of any subsequently performed planarization processes, such as CMP processes and the like, can be severely impacted, as discussed in detail below.
FIG. 1f shows the illustrative prior art process of FIG. 1e in a further advanced manufacturing stage. As shown in FIG. 1f, a planarization process 140, such as a CMP process and the like, may be performed to remove the horizontal portion of the layer of conductive contact material 113 formed outside of the TSV openings 110 from above the wafer 100. Furthermore, in some embodiments the horizontal portions of the isolation layer 111 formed above the wafer 100 and outside of the TSV openings 110 may also be removed during the planarization process 140. Moreover, the thickness of the hardmask layer 107, which as noted previously may act as a CMP stop layer, may also be reduced during the planarization process 140. After completion of the planarization process 140, additional processing of the front side 100f of the wafer 100 may be performed, such as forming metallization layers and the like above the TSV's 120 and the contact structure layer 104. Thereafter, the wafer 100 may be thinned from the back side 100b so as to reduce the thickness of the substrate 101 (indicated in FIG. 1f by dashed line 101t) and expose the bottom surfaces 120b of the TSV's 120 in preparation for wafer stacking and substrate bonding—i.e., 3D integrated circuit assembly.
As noted previously, a layer of conductive contact material 113 having large amount of overburden 113b formed outside of the TSV openings 110 may substantially impact the overall effectiveness of the planarization process 140. Due to this large amount of overburden 113b, highly aggressive CMP parameters may be necessary to ensure complete removal of the excess conductive contact material 113 from above the horizontal surfaces of the wafer 100. As shown in FIG. 1f, these highly aggressive CMP parameters may cause the presence of the depression 114 (see FIG. 1e) to translate into a dished region 115 having a depth 115a at the upper end of each TSV 120 after completion of the planarization process 140—a phenomenon well known in the art of chemical mechanical polishing. In some embodiments, the depth 115a of the dished region 115 may exceed 100 nm or more, and under certain conditions—such as the depth 114a of the original depression 114, the CMP recipe, and the like—the depth 115a may be as large as 200 nm, or even greater. Furthermore, the presence of the dished region 115 in the TSV's 120 may translate into additional defects in the layers of a metallization system (not shown) subsequently formed above the TSV's 120 and the contact structure layer 104, such as voids, gaps, and additional depressions and/or dished regions, thereby potentially leading to decreased product yield and reduced product performance.
TABLE 1Approximate Bulk Linear Coefficients ofThermal Expansion for Selected MaterialsConductiveCTESemiconductor-BasedCTEMaterial(μm/m/° C.)Material(μm/m/° C.)Tungsten4.3Silicon2.6Tantalum6.5Germanium5.8Titanium8.6Silicon-Germanium3.4-5.0Platinum9.0Silicon Dioxide0.5Cobalt12.0Silicon Nitride3.3Nickel13.0Silicon Carbide4.0Gold14.2Copper16.6Silver19.5Aluminum22.2
Additionally, due to the significant difference in the coefficient of thermal expansion (CTE) between copper—which may be a major material constituent in some TSV's—and that of many of the materials commonly used in semiconductor processing, such as silicon, germanium, silicon dioxide, silicon nitride and the like, significant thermal stresses may be induced in the circuit elements surrounding TSV's during normal operation. For example, Table 1 above lists some approximate representative values of the bulk linear coefficient of thermal expansion (CTE) of several materials that may commonly be used in the manufacture of semiconductor devices, graphically illustrating the difference between the CTE of conductive materials that might commonly be used for forming TSV's, and that of the semiconductor-based materials which might comprise the majority of many device layers and circuit elements.
As can be seen from the approximate CTE data presented in Table 1 above, the coefficient of expansion of a typical conductive material such as copper ranges anywhere from approximately 3 to 30 times greater than the CTE of typical semiconductor-based materials, which during normal device operation could result in a significant differential thermal expansion, and commensurately high thermal stresses in the areas surrounding TSV's. Additionally, due to the tremendous size disparity between that of a typical TSV (sizes on the order of μm's) vs. that of a typical modern integrated circuit elements (sizes on the order of nm's)—a disparity that may approach three orders of magnitude—the thermal stresses induced in any circuit elements proximate the TSV's may be even further exacerbated. Furthermore, as noted previously, TSV's may typically be used in 3D integrated circuit layouts to provide electrical interconnection between various stacked chips, and as such the amount power transmitted through the TSV's may result in a significant temperature increase in the area surrounding the TSV's during normal operation of a stacked chip. Each of these factors—relative size disparity between TSV's and circuit elements, difference in CTE, and elevated temperature during chip operation—may have a significant effect on the level of thermal stress 125 (see FIG. 10 that may be induced in the circuit elements 203 near the TSV's, and a subsequent reduction in device performance and overall chip life. Moreover, these problems may be compounded in and around the device layers and contact structure layers of a chip, which may comprise low-k dielectric materials having a lower overall material strength and a lower resistance to thermally induced stresses, possibly resulting in further reduced product quality and performance.
Accordingly, there is a need to implement new design strategies to address the manufacturing and performance issues associated with the overall configuration of TSV's, as well and the typical methods used for forming TSV's. The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.